1. Field of the Invention
This invention relates generally to data processing systems and more particularly to the testing of data processing systems, especially those having multiple central processing units.
2. Description of the Related Art
It is known in the related art to test the integrity of a central processing unit of a data processing system by introducing appropriate software sequences of instructions and programs into the main memory. Subsequently, the programs are entered into the central processing unit, the programs are executed, and the results of the program execution are compared to expected results to verify the operation of the data processing system. This procedure has the disadvantage that results of the program execution stored in main memory consists of data that has potentially been compromised. In the configuration where more than one central processing unit has access to the main memory, erroneous information can be transferred to the central processing units not under test. It would therefore be desirable to provide a method of utilizing sequences of instructions and programs to test a central processing unit when the central processing unit is isolated from the remainder of the data processing unit. However, central processing units are typically arranged to accept information only through an interface port.
It is also known in the prior art to provide a maintenance panel with conductive paths coupled to selected locations of the central processing unit. From the maintenance panel, pre-selected registers can have predetermined data sequences entered therein. The maintenance panel can then cause the central processing unit to perform operations corresponding to the predetermined data sequences, e.g., by initiating a predetermined number of system clock cycles. The accuracy of the central processing unit operations can be determined by extracting data sequences from the selected central processing unit locations by means of the maintenance panel and comparing these sequences with expected data sequences in the appropriate registers. This verification technique has several disadvantages. One disadvantage is that the process of loading preselected registers can be relatively slow. Furthermore, this procedure is artificial and does not exemplify the typical operation of a central processing unit. A further disadvantage is that aditional manipulation of data resulting from transfer to and from the maintenance panel can introduce ambiguities that may obscure the origin of the errors.